1. Field of the Invention
The invention relates to a shift register, and more particularly to a control method for compensating for shifting of threshold voltage of transistors in the shift register.
2. Description of the Related Art
In current liquid crystal display panels, gate drivers and drain drivers are arranged to provide scan signals and data signals. In order to decrease costs, a shift register which has the same function as a gate driver is arranged in a glass panel. Most shift registers are formed by amorphous silicon thin-film processes. When a display panel is lit, transistors of a shift register in the display panel are affected by stress, and the display panel thus operates irregularly.
FIG. 1 shows a conventional shift register unit of a shift register. FIG. 2 is a timing chart of signals of the shift register unit in FIG. 1. Referring to FIGS. 1 and 2, a shift register unit 1 is controlled by clock signals CK and XCK opposite to each other, that is, the clock signals CK and XCK have inverse phases, and are coupled to a low voltage source Vss. The shift register unit 1 receives output signals SN−1 and SN+1 respectively from the previous shift register unit and the next shift register unit and generates an output signal SN. At a time point P10, the output signal SN−1 is activated, that is, the output signal SN−1 is at a high level, and a transistor T10 is turned on. A voltage VN10 at a node N10 is changed to a high level according to the output signal SN−1 to turn on transistors T11 and T12. At this time, since the clock signal CK is at a low level and the transistor T12 is turned on, a voltage VN11 at a node N11 is at a low level to turn off a transistor T13. A transistor T15 is turned on by the clock signal XCK with a high level, and the output signal SN is de-activated, that is, the output signal SN is at a low level.
At a time point P11, the output signal SN−1 is de-activated, and the transistor T10 is turned off. The clock signal CK is changed to a high level. In the period between the time points P11 and P12, the clock signal CK with the high level couples to the node N10 through a capacitor C10 and the transistor T13, so that the voltage VN10 at the node N10 is raised to a higher level according to the clock signal CK to turn on the transistors T11 and T12. According to the low voltage source Vss and the turned-on transistor T12, the voltage VN11 at the node N11 remains at the low level to turn off the transistor T13. The clock signal CK with the high level is transmitted to an output node N12 through the turned-on transistor T11 to serve as the output signal SN, in other words, the output signal SN is activated. The clock signal XCK with a low level turns off a transistor T15, and the voltage VN11 with the low level turns off a transistor T16. Accordingly, the output signal SN can stably remain in the activated state.
At a time point P12, the clock signal CK is changed to a low level, and the output signal SN+1 is activated to turn on the transistor T14. The voltage VN10 at the node N10 is gradually decreased according to the low voltage source Vss to turn off the transistors T11 and T12. At this time, the clock signal XCK with a high level turns on the transistor T15, so that the voltage of the low voltage source Vss is provided to the output node N12 to serve as the output signal SN, in other words, the output signal SN is de-activated.
At a time point P13, the clock signal CK is changed to a high level, and the voltage VN11 at the node N11 is changed to a high level to turn on the transistor T13. Thus, the voltage N10 remains at a low level. Moreover, the voltage VN11 with the high level turns on the transistor T16, so that the output signal SN remains in the de-activated state. After the time point P13, the shift register unit 1 operates according to the clock signal CK and XCK. The voltage VN10 at the node N11 is switched between a high level and a low level.
It is assumed that the high level and the low level of the clock signal CK is 15V and −9V respectively, and the voltage of the low voltage source Vss is −7V. When the clock signal CK is at the high level to turn on the transistor T13, the voltage difference between a gate and a source of the transistor T13 is 22V. If the gate-source voltage Vgs of the transistor T13 is under positive base stress for a long time, the threshold voltage of the transistor T13 shifts, and the voltages VN10 and VN11 become irregular, as shown by the dotted line in VN10 and VN11 in FIG. 2. Similarly, if the gate-source voltages Vgs of the transistors T11, T12, and T14-16 are under positive base stress for a long time, their threshold voltages also shift. Thus, when the threshold voltages of the transistors in the shift register unit 1 shift, the shift register unit 1 operates irregularly and outputs an incorrect output signal SN.